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flash memory 1 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m document title 256m x 8 bit / 128m x 16 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 remark advance history 1. initial issue 1. i ol (r/b ) of 1.8v device is changed. -min. value: 7ma -->3ma -typ. value: 8ma -->4ma 1. 5th cycle of id is changed : 40h --> 44h 1. add wsop package dimensions. 1. add two-k9k2gxxu0m-ycb0/yib0 stacked package 1. min valid block of k9w4gxxu1m-ycb0/yib0 is changed . - min. 4016 --> 4036 1. each k9k2gxxx0m chip in the k9w4gxxu1m has maximum 30 invalid blocks. 2. k9w4gxxu1m?s id is changed (before) (after) 1. add the rp vs tr ,tf & rp vs ibusy graph for 1.8v device (page 36) 2. add the data protection vcc guidence for 1.8v device - below about 1.1v. (page 37) the min. vcc value 1.8v devices is changed. k9k2gxxq0m : vcc 1.65v~1.95v --> 1.70v~1.95v device 2nd cycle 3rd cycle 4th cycle 5th cycle k9w4g08u1m dch c3 15h 4ch k9w4g16u1m cch c3 55h 4ch device 2nd cycle 3rd cycle 4th cycle 5th cycle k9w4g08u1m dah c1 15h 44h k9w4g16u1m cah c1 55h 44h draft date aug. 30.2001 nov. 5.2001 jan. 23. 2002 may.29.2002 aug.13.2002 aug. 22.2002 nov. 07.2002 nov. 22.2002 mar. 6.2003
flash memory 2 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m document title 256m x 8 bit / 128m x 16 bit nand flash memory revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung elec tronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near your office. revision no 0.9 1.0 1.1 1.2 1.3 1.4 remark history pb-free package is added. k9k2g08u0m-fcb0,fib0 k9k2g08q0m-pcb0,pib0 k9k2g08u0m-pcb0,pib0 k9k2g16u0m-pcb0,pib0 k9k2g16q0m-pcb0,pib0 k9w4g08u1m-pcb0,pib0,ecb0,eib0 k9w4g16u1m-pcb0,pib0,ecb0,eib0 errata is added.(front page)-k9k2gxxq0m twc twp twh trc treh trp trea tcea specification 45 25 15 50 15 25 30 45 relaxed value 80 60 20 80 20 60 60 75 1. the 3rd byte id after 90h id read command is don?t cared. the 5th byte id after 90h id read command is deleted. new package dimension is added.(k9w4gxxu1m-kxb0/exb0) 1. min valid block of k9w4gxxu1m-ycb0/yib0 is changed . - min. 4036 --> 4016 2. note is added. (vil can undershoot to -0.4v and vih can overshoot to vcc +0.4v for durations of 20 ns or less.) ac parameters are changed-k9k2gxxq0m twc twp twh trc treh trp trea tcea before 45 25 15 50 15 25 30 45 after 80 60 20 80 20 60 60 75 draft date mar. 13.2003 mar. 17.2003 apr. 9. 2003 apr. 15. 2003 apr. 18. 2003 aug. 5. 2003
flash memory 3 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m general description features ? voltage supply -1.8v device(k9k2gxxq0m): 1.7v~1.95v -3.3v device(k9xxgxxuxm): 2.7 v ~3.6 v ? organization - memory cell array -x8 device(k9k2g08x0m) : (256m + 8,192k)bit x 8bit -x16 device(k9k2g16x0m) : (128m + 4,096k)bit x 16bit - data register -x8 device(k9k2g08x0m): (2k + 64)bit x8bit -x16 device(k9k2g16x0m): (1k + 32)bit x16bit - cache register -x8 device(k9k2g08x0m): (2k + 64)bit x8bit -x16 device(k9k2g16x0m): (1k + 32)bit x16bit ? automatic program and erase - page program -x8 device(k9k2g08x0m): (2k + 64)byte -x16 device(k9k2g16x0m): (1k + 32)word - block erase -x8 device(k9k2g08x0m): (128k + 4k)byte -x16 device(k9k2g16x0m): (64k + 2k)word ? page read operation - page size - x8 device(k9k2g08x0m): 2k-byte - x16 device(k9k2g16x0m) : 1k-word - random read : 25 s(max.) - serial access 1.8v device(k9k2gxxq0m): 80ns(min.) 3.3v device(k9xxgxxuxm): 50ns(min.) 256m x 8 bit / 128m x 16 bit nand flash memory ? fast write cycle time - program time : 300 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years ? command register operation ? cache program operation for high performance program ? power-on auto-read operation ? intelligent copy-back operation ? unique id for copyright protection ? package : - k9k2gxxx0m-ycb0/yib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9k2g08u0m-vcb0/vib0 48 - pin wsop i (12x17x0.7mm) - k9k2gxxx0m-pcb0/pib0 48 - pin tsop i (12 x 20 / 0.5 mm pitch)- pb-free package - k9k2g08u0m-fcb0/fib0 48 - pin wsop i (12x17x0.7mm)- pb-free package * k9k2g08u0m-v,f(wsopi ) is the same device as k9k2g08u0m-y,p(tsop1) except package type. - k9w4gxxu1m-ycb0,pcb0/yib0,pib0 : two k9k2g08u0m stacked. 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9w4gxxu1m-kcb0,ecb0/kib0,eib0 : two k9k2g08u0m stacked. 48 - pin tsop i (12 x 17 / 0.5 mm pitch) offered in 256mx8bit or 128mx16bit, the k9k2gxxx0 m is 2g bit with spare 64m bit capacity. its nand cell provides the most cost - effective solution for the solid state mass storage ma rket. a program operation can be performed in typical 300 s on the 2112-byte(x8 device) or 1056-word(x16 device) page and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) or 64k- word(x16 device) block. data in the data page can be read out at 80ns(1.8v device) or 50ns(3.3v device) cycle time per byte(x8 device) or word(x16 device). the i/o pins serve as the ports for address and data input/output as well as command input. the on -chip write controller automates all program and er ase functions including pulse repetition, where required, and internal verificatio n and margining of data. even the write-intensive systems can take advantage of the k9k2gxxx0m s extended reliability of 100k program/ erase cycles by providing ecc(error corr ecting code) with real time mapping-out algorithm. the k9k2gxxx0m is an optimum solu- tion for large nonvolatile storage applications such as solid state file st orage and other portable appl ications requiring non- volatility. an ultra high density solution having two 2gb stacked with two chip selects is also available in standard tsopi package. product list part number vcc range organization pkg type k9k2g08q0m-y,p 1.7 ~ 1.95v x8 tsop1 K9K2G16Q0M-Y,p x16 k9xxg08uxm-y,p,k,e 2.7 ~ 3.6v x8 k9xxg16uxm-y,p,k,e x16 k9k2g08u0m-v,f x8 wsop1
flash memory 4 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m pin configuration (tsop1) k9k2gxxx0m-ycb0,pcb0/yib0,pib0 x8 x16 x16 x8 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c pre vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c r/b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 n.c pre vcc n.c n.c n.c i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss
flash memory 5 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m pin configuration (wsop1) k9k2g08u0m-vcb0,fcb0/vib0,fib0 package dimensions 48-pin lead/lead free plastic very very th in small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0.20 +0.07 -0.03 0.16 +0.07 -0.03 0.50typ (0.50 0.06) #48 #25 12.00 0.10 0.10 +0.075 -0.035 0.58 0.04 0.70 max (0.1min) 17.00 0.20 0 ~ 8 0.45~0.75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c
flash memory 6 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m pin configuration (tsop1) k9w4g08u1m-ycb0,pcb0/yib0,pib0 package dimensions 48-pin lead/lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.16 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.05 0.03 0.002 0.02 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c pre vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c x16 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c x16 vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 n.c pre vcc n.c n.c n.c i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss x8 x8
flash memory 7 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m pin configuration (tsop1) package dimensions 48-pin lead/lead free plastic thin small out-line package type (i) 48 - tsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0.20 +0.07 -0.03 0.16 +0.07 -0.03 0.50typ (0.50 0.06) #48 #25 12.00 0.10 0.15 +0.075 -0.035 1.00 0.03 1.15 max (0.02min) 17.00 0.20 0 ~ 8 0.45~0.75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c pre vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c x16 n.c n.c n.c n.c n.c r/b2 r/b1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c x16 vss i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 n.c pre vcc n.c n.c n.c i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 vss x8 x8 k9w4g08u1m-kcb0,ecb0/kib0,eib0 48-pin tsop1 12mm x 17mm
flash memory 8 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m pin description note : connect all v cc and v ss pins of each device to common power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~ i/o 7 (k9k2g08x0m) i/o 0 ~ i/o 15 (k9k2g16x0m) data inputs/outputs the i/o pins are used to input command, address and dat a, and to output data during read operations. the i/ o pins float to high-z when the chip is des elected or when the outputs are disabled. i/o8 ~ i/o15 are used only in x16 org anization device. since command input and address input are x8 oper- ation, i/o8 ~ i/o15 are not used to input command & address. i/o8 ~ i/o15 are used only for data input and output. cle command latch enable the cle input controls the activating path for comm ands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for addres s to the internal address registers. addresses are latched on the rising edge of we with ale high. ce / ce 1 chip enable the ce / ce 1 input is the device selection control. when the device is in the busy state, ce / ce 1 high is ignored, and the device does not return to standby mode in program or erase opertion. regarding ce / ce 1 control during read operation, refer to ?page read? section of device operation . ce 2 chip enable the ce 2 input enables the second k9k2gxxu0m re read enable the re input is the serial data-out control, and when active drives the data onto t he i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands , address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection du ring power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b / r/b 1 ready/busy output the r/b / r/b 1 output indicates the status of the device operat ion. when low, it indicates that a program, erase or random read operation is in process and retu rns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. r/b 2 ready/busy output the r/b 2 output indicates the status of the second k9k2gxxu0m pre power-on read enable the pre controls auto read operation executed duri ng power-on. the power-on auto-read is enabled when pre pin is tied to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected.
flash memory 9 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m 2k bytes 64 bytes figure 1-1. k9k2g08x0m (x8) functional block diagram figure 2-1. k9k2g08x0m (x8) array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 5th cycle a 28 *l *l *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 28 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss 128k pages (=2,048 blocks) 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 2048 blocks = 2112 mbits row address page register ale pre 2048m + 64m bit nand flash array (2048 + 64)byte x 131072 y-gating cache register row address column address column address data register & s/a row address
flash memory 10 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m 1k words 32 words figure 1-2. k9k2g16x0m (x16) functional block diagram figure 2-2. k9k2g16x0m (x16) array organization note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional i nput of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o8 ~ 15 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 *l 2nd cycle a 8 a 9 a 10 *l *l *l *l *l *l 3rd cycle a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 18 *l 4th cycle a 19 a 20 a 21 a 22 a 23 a 24 a 25 a 26 *l 5th cycle a 27 *l *l *l *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 11 - a 27 a 0 - a 10 command ce re we cle wp i/0 0 i/0 15 v cc v ss 128k pages (=2,048 blocks) 1k words 16 bit 32 words 1 block = 64 pages (64k + 2k) word i/o 0 ~ i/o 15 1 page = (1k + 32)words 1 block = (1k + 32)word x 64 pages = (64k + 2k) words 1 device = (1k+32)word x 64pages x 2048 blocks = 2112 mbits row address page register ale pre 2048m + 64m bit nand flash array (1024 + 32)word x 131072 y-gating cache register row address column address column address data register & s/a row address
flash memory 11 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m product introduction the k9k2gxxx0m is a 2112mbit(2,214,592,512 bit) memory or ganized as 131,072 rows(pages) by 2112x8(x8 device) or 1056x16(x16 device) columns. spare 64(x8) or 32(x16) columns ar e located from column address of 2048~2111(x8 device) or 1024~1055(x16 device). a 2112-byte(x8 device) or 1056-word(x16 device) data register and a 2112-byte(x8 device) or 1056- word(x16 device) cache register are serially connected to eac h other. those serially connected registers are connected to memo ry cell arrays for accommodating data transfer between the i/o buffers and memory cells during page read and page program opera- tions. the memory array is made up of 32 cells that are serially connected to form a nand structure. each of the 32 cells resid es in a different page. a block consists of two nand structured stri ngs. a nand structure consists of 32 cells. total 1081344 nand cell s reside in a block. the program and read operations are executed on a page basis, while the erase operation is executed on a blo ck basis. the memory array consists of 2048 separately erasable 128k-b yte(x8 device) or 64k-word(x16 device) blocks. it indicates that the bit by bit erase operation is prohibited on the k9k2gxxx0m. the k9k2gxxx0m has addresses multiplexed into 8 i/os(x16 device case : lower 8 i/os). this sc heme dramatically reduces pin counts and allows system upgrades to fu ture densities by maintaining consistency in system board design. command, address and data are all written through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiple x command and address respectively, via the i/o pins. some com- mands require one bus cycle. for example, reset command, stat us read command, etc require just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for exec u- tion. the 256m byte(x8 device) or 128m wo rd(x16 device) physical space requires 29(x8 ) or 28(x16) addresses, thereby requiring four cycles for addressing: 2 cycles of column address, 3 cy cles of row address, in that order. page read and page program nee d the same four address cycles following the required command i nput. in block erase operation, however, only the two row address cycles are used. device operations are sele cted by writing specific commands into the command register. table 1 defines the spe cific commands of the k9k2gxxx0m. the device provides cache program in a blo ck. it is possible to write data into the cache registers while data stored in data r egisters are being programmed into memory cells in cache program mode. the program performace may be dr amatically improved by cache program when there are lots of pages of data to be programmed. the device embodies power-on auto-read featur e which enables serial access of data of the 1st page without command and address input after power-on. in addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the exter nal buffer memory. since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. table 1. command sets note : 1. random data input/output can be executed in a page. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h cache program 80h 15h copy-back program 85h 10h block erase 60h d0h random data input * 85h - random data output * 05h e0h read status 70h o
flash memory 12 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m dc and operating characteristics (recommended operating cond itions otherwise noted.) note : v il can undershoot to -0.4v and v ih can overshoot to v cc +0.4v for durations of 20 ns or less. parameter symbol test conditions k9k2gxxq0m(1.8v) k9xxgxxuxm(3.3v) unit min typ max min typ max operat- ing current page read with serial access i cc 1 trc=50ns, ce =v il i out =0ma - 10 20 - 15 30 ma program i cc 2 - - 10 20 - 15 30 erase i cc 3 - - 10 20 - 15 30 stand-by current(ttl) i sb 1ce =v ih , wp =pre =0v/v cc --1--1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =pre =0v/v cc - 20 100 - 20 100 a input leakage current i li v in =0 to vcc(max) - - 20 - - 20 output leakage current i lo v out =0 to vcc(max) - - 20 - - 20 input high voltage v ih* -v cc -0.4 - v cc + 0.3 2.0 - v cc +0.3 v input low voltage, all inputs v il* - -0.3 - 0.4 -0.3 - 0.8 output high voltage level v oh k9k2gxxq0m:i oh =-100 a k9xxgxxuxm:i oh =-400 a vcc-0.1 - - 2.4 - - output low voltage level v ol k9k2gxxq0m :i ol =100ua k9xxgxxuxm :i ol =2.1ma --0.1--0.4 output low current(r/b )i ol (r/b ) k9k2gxxq0m :v ol =0.1v k9xxgxxuxm :v ol =0.4v 34-810-ma recommended operating conditions (voltage reference to gnd, k9xxgxxxxm-xcb0 : t a =0 to 70 c, k9xxgxxxxm-xib0 : t a =-40 to 85 c) parameter symbol k9k2gxxq0m(1.8v) k9xxgxxuxm(3.3v) unit min typ. max min typ. max supply voltage v cc 1.7 1.8 1.95 2.7 3.3 3.6 v supply voltage v ss 000000v absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins. during trans itions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc, +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet . exposure to absolute maximum rating conditions for extended peri ods may affect reliability. parameter symbol rating unit k9k2gxxq0m(1.8v) k9xxgxxuxm(3.3v) voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 temperature under bias k9xxgxxxxm-xcb0 t bias -10 to +125 c k9xxgxxxxm-xib0 -40 to +125 storage temperature k9xxgxxxxm-xcb0 t stg -65 to +150 c k9xxgxxxxm-xib0 short circuit current ios 5 ma
flash memory 13 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m capacitance ( t a =25 c, v cc =1.8v/3.3v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition max unit k9k2gxxx0m k9w4gxxu1m input/output capacitance c i/o v il =0v 20 40 pf input capacitance c in v in =0v 20 40 pf valid block note : 1. the device may include invalid blocks when first shipped. additional inva lid blocks may develop while being used. the number of valid bloc ks is pre- sented with both cases of invalid blocks considered. invalid bl ocks are defined as blocks that contain one or more bad bits . do not erase or pro- gram factory-marked bad blocks. refer to the attached technical notes for appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is guaranteed to be a valid block, does not require error correction u p to 1k program/erase cycles. * : each k9k2gxxx0m chip in the k9w4gxxu1m has maximum 40 invalid blocks. parameter symbol min max unit k9k2gxxx0m valid block number n vb 2008 2048 blocks k9w4gxxu1m valid block number n vb 4016* 4096* blocks ac test condition (k9xxgxxxxm-xcb0 :ta=0 to 70 c, k9xxgxxxxm-xib0:ta=-40 to 85 c k9k2gxxq0m : vcc=1.70v~1.95v , k9xxgx xuxm : vcc=2.7v~3.6v unless otherwise noted) parameter k9k2gxxq0m k9xxgxxuxm input pulse levels 0v to vcc 0.4v to 2.4v input rise and fall times 5ns 5ns input and output timing levels vcc/2 1.5v k9k2gxxq0m:output load (vcc:1.8v +/-10%) k9xxgxxuxm:output load (vcc:3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9xxgxxuxm:output load (vcc:3.3v +/-10%) - 1 ttl gate and cl=100pf mode selection note : 1. x can be v il or v ih. 2. wp and pre should be biased to cmos high or cmos low for standby. cle ale ce we re wp pre mode hll hxx read mode command input l h l h x x address input(5clock) hll hhx write mode command input l h l h h x address input(5clock) l l l h h x data input l l l h x x data output x x x x h x x during read(busy) x x x x x h x during program(busy) x x x x x h x during erase(busy) x x (1) x x x l x write protect xxhxx 0v/v cc (2) 0v/v cc (2) stand-by
flash memory 14 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m ac characteristics for operation note : 1. if reset command(ffh) is written at ready stat e, the device goes into busy for maximum 5us. parameter symbol min min max max unit k9k2gxxq0m k9k2gxxu0m k9k2gxxq0m k9k2gxxu0m data transfer from cell to register t r - - 25 25 s ale to re delay t ar 10 10 - - ns cle to re delay t clr 10 10 - - ns ready to re low t rr 20 20 - - ns re pulse width t rp 60 25 - - ns we high to busy t wb - - 100 100 ns read cycle time t rc 80 50 - - ns re access time t rea - - 60 30 ns ce access time t cea - - 75 45 ns re high to output hi-z t rhz - - 30 30 ns ce high to output hi-z t chz - - 20 20 ns re or ce high to output hold t oh 15 15 - - ns re high hold time t reh 20 15 - - ns output hi-z to re low t ir 00 - -ns we high to re low t whr 60 60 - - ns device resetting time (read/program/erase) t rst -- 5/10/500 (1) 5/10/500 (1) s ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be mi nimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol min max unit k9k2gxxq0m k9k2gxxu0m k9k2gxxq0m k9k2gxxu0m cle setup time t cls 00 - -ns cle hold time t clh 10 10 - - ns ce setup time t cs 00 - -ns ce hold time t ch 10 10 - - ns we pulse width t wp 60 25 (1) --ns ale setup time t als 00 - -ns ale hold time t alh 10 10 - - ns data setup time t ds 20 20 - - ns data hold time t dh 10 10 - - ns write cycle time t wc 80 45 - - ns we high hold time t wh 20 15 - - ns program / erase characteristics note : 1. max. time of t cbsy depends on timing between internal program completion and data in parameter sym- min typ max unit program time t prog - 300 700 s dummy busy time for cache program t cbsy 3 700 s number of partial program cycles in the same page main array nop --4cycles spare array - - 4 cycles block erase time t bers -23ms
flash memory 15 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the infor- mation regarding the invalid block(s) is so called as the invali d block information. devices with invalid block(s) have the sam e quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid bl ock(s) does not affect the per for- mance of valid block(s) because it is isolated from the bit line and the common s ource line by a select transistor. the system design must be able to mask out the invalid block(s) via address mappi ng. the 1st block, which is placed on 00h block address, is guar an- teed to be a valid block, does not require er ror correction up to 1k program/erase cycles. all device locations are erased(ffh for x8, ffffh for x16) except locations where the invalid block(s) information is written p rior to shipping. the invalid block(s) status is defined by the 1st byte(x8 dev ice) or 1st word(x16 device) in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid bl ock has non-ffh(x8) or non-ffffh(x16) data at the column address of 2048(x8 device) or 1024(x16 device). since t he invalid block information is also erasab le in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the invalid block(s) based on the orig inal invalid block information and create the invalid block table via the following suggested flow chart(figure 3). any intentional erasure of the original invalid block information is prohibited. * check "ffh( or ffffh)" at the column address figure 3. flow chart to create invalid block table. start set block address = 0 check "ffh increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block 2048(x8 device) or 1024(x16 device) or ffffh" ?
flash memory 16 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data fail program completed or r/b = 1 ? program error yes no yes * program error pass : if program operation r esults in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation within its life time, additional invalid blocks may develop with nand flash memory. refer to the qualification report for the a ctual data.the following possible failure modes s hould be considered to implement a highly reli able system. in the case of status rea d fail- ure after erase or program, block replacem ent should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replac ement can be executed with a page- sized buffer by finding an erased empty block and reprogramming the current target data and copying t he rest of the replaced block.to improve the efficiency of m em- ory space, it is recommended that the read or verification fail ure due to single bit error be re claimed by ecc without any bloc k replacement. the said additional block failure ra te does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after pr ogram) --> block replacement or ecc correction read single bit failure ve rify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection write 30h
flash memory 17 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) write 30h block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { 1st (n-1)th nth (page) { an error occurs.
flash memory 18 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m system interface using ce don?t-care. for an easier system interface, ce may be inactive during the data-loading or se rial access as shown below. the internal 2112byte(x8 device) or 1056word(x16 device) data registers are utilized as separate buffers for this operation and the system design gets more flexible. in addition, for voice or audio applications which use slow cycle time on t he order of u-seconds, de-activa ting ce during the data-loading and serial access would prov ide significant savings in power consumption. figure 4. program operation with ce don?t-care. ce we t wp t ch t cs address(4cycles) 80h data input ce cle ale we data input ce don?t-care 10h address(4cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. read operation with ce don?t-care. 30h i/ox i/ox
flash memory 19 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m k9xxg16xxm : i/o 8 ~ 15 must be set to "0" k9xxg16xxm : i/o 8 ~ 15 must be set to "0" command latch cycle ce we cle ale command address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh note device i/o data address i/ox data in/out col. add1 col. add2 row add1 row add2 row add3 k9k2g08x0m(x8) i/o 0 ~ i/o 7 ~2112byte a0~a7 a8~a11 a12~a19 a20~a27 a28 k9k2g16x0m(x16) i/o 0 ~ i/o 15 ~1056word a0~a7 a8~a10 a11~a18 a19~a26 a27 i/ox ce we cle ale col. add1 t c l s t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh
flash memory 20 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m input data latch cycle ce cle we din 0 din 1 din final* ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp serial access cycle after read (cle=l, we =h, ale=l) re ce r/b dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz* notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. t cea i/ox i/ox notes : din final means 2112(x8) or 1056(x16) t chz* t rhz*
flash memory 21 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m status read cycle ce we cle re 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir* t oh t oh t whr t cea t cls k9xxg16xxm : i/o 8 ~ 15 must be set to "0" i/ox t chz* t rhz*
flash memory 22 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m read operation (intercepted by ce ) ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h read operation ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox i/ox col. add1 col. add2 row add1 row add2 row add3 row add3 t oh
flash memory 23 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h 05h column address dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 t clr dout m e0h t whr t rea
flash memory 24 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m x8 device : m = 2112byte x16 device : m = 1056word page program operation ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3
flash memory 25 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m page program operation with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3
flash memory 26 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m copy-back program operation with random data input ce cle r/b we ale re 00h 70h i/o 0 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n i/ox col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 row add3 row add3
flash memory 27 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m cache program operation (available only within a block) ce cle r/b we ale re 80h din n din 15h m serial data input command column address serial input program max. 63 times repeatable tcbsy twb twc command last page input & program t cbsy : max. 700us (dummy) din n din 10h tprog twb i/o 80h col add1,2 & row add1,2 r/b data address & data input 15h 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h ex.) cache program t cbsy t cbsy t cbsy t prog program confirm command (true) 80h 70h 70h m row address i/ox i/ox col add1 col add2 row add1 row add2 col add1 col add2 row add1 row add2 row add3 row add3
flash memory 28 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3
flash memory 29 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m read id operation ce cle we ale re 90h read id command maker code device code 00h ech device t rea address. 1cycle xxh 4th cyc.* id defintition table 90 id : access command = 90h description 1 st byte 2 nd byte 3 rd byte 4 th byte maker code device code don?t care page size, block size, spare size, organization i/ox t ar code* device device code*(2nd cycle) 4th cycle* k9k2g08q0m aah 15h k9k2g08u0m dah 15h k9k2g16q0m bah 55h k9k2g16u0m cah 55h k9w4g08u1m same as each k9k2g08u0m in it k9w4g16u1m same as each k9k2g16u0m in it
flash memory 30 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m 4th id data description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb reserved reserved 0 0 0 1 1 0 1 1 blcok size (w/o redundant area ) 64kb 128kb 256kb reserved 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns 30ns reserved reserved 0 0 1 1 0 1 0 1
flash memory 31 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m device operation page read upon initial device power up, the device defaults to read mode.this operation is also initiated by writing 00h-30h to the comma nd register along with five address cycles. in two consecutive read operations, the second one doesn?t need 00h command, which fiv e address cycles and 30h command initiates that operation. once the command is latched, it does not need to be written for the fo llow- ing page read operation. two types of operations are available : random read, serial page read . the random read mode is enabled when the page address is changed. the 2112 bytes(x8 device) or 1056 words(x16 device) of data within the selected page are transferred to the data registers in less than 25 s(t r ). the system controller can detect the comple- tion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 80ns(1.8v device) or 50ns(3.3v dev ice) cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the co nsecutive sequential data by writing random data output command. the column address of next data, which is going to be out, ma y be changed to the address which follows random data output com- mand. random data output can be operated multiple time s regardless of how many times it is done in a page. figure 6. read operation address(5cycle) 00h col add1,2 & row add1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox
flash memory 32 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m figure 7. random data output in a page address 00h data output r/b re t r 30h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field page program the device is programmed basically on a page bas is, but it does allow multiple partial page programing of a byte or consecutive bytes up to 2112(x8 device) or words up to 1056(x 16 device), in a single page program cycle. the number of consecutive partial page p ro- gramming operation within the same page without an interveni ng erase operation must not exceed 4 times for main array(x8 device:1time/512byte, x16 device:1time/256word) and 4 times for spare array(x8 device:1time/16by te, x16 device:1time/8word). the addressing should be done in sequential order in a block. a p age program cycle consists of a serial data loading period in which up to 2112bytes(x8 device) or 1056words(x16 device) of data may be loaded into the data register, followed by a non-volatile pr o- gramming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the five cycle address input s and then serial data loading. the bytes other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which wi ll be entered, may be changed to the address which follows rando m data input command(85h). random data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone wit hout previously entering the serial data will not initiate the programming process. the internal write state controller automat ically executes the algorithm s and tim- ings necessary for program and verify, thereb y freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the status r egister. the system controller can detect the completion of a p ro- gram cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the p age program is complete, the write status bit(i/o 0) may be checked(figure 8). the internal write verify detects only errors for "1"s that are no t successfully programmed to "0"s. the com mand register remains in read status command mode until an other valid command is written to the command register. figure 8. program & read status operation 80h r/b address & data input i/o 0 pass data 10h 70h fail t prog i/ox i/ox col add1,2 & row add1,2,3 "0" "1"
flash memory 33 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m cache program figure 9. random data input in a page 80h r/b address & data input i/o 0 pass 10h 70h fail t prog 85h address & data input cache program is an extension of page progr am, which is executed with 2112byte(x8 device) or 1056word(x16 device) data regis- ters, and is available only within a block. since the device has 1 page of cache me mory, serial data input may be executed whi le data stored in data register are programmed into memory cell. after writing the first set of data up to 2112byte(x8 device) or 1056word(x16 device) into the selected cache registers, cache pro- gram command (15h) instead of actual page program (10h) is inputt ed to make cache registers free and to start internal program operation. to transfer data from cache registers to data register s, the device remains in busy state for a short period of time (tcbsy) and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out wh en cache registers become ready by polling the cache-busy sta- tus bit(i/o 6). pass/fail status of only t he previouse page is available upon the return to ready state. when the next set of d ata is inputted with the cache program command, tcbsy is affected by the progress of pending internal programming. the programming of the cache registers is initiated only w hen the pending program cycle is finished and t he data registers are available for the t ransfer of data from cache registers. the status bit(i/o5) for internal r eady/busy may be polled to identify the completion of internal pr ogram- ming. if the system monitors the progress of programming only with r/b , the last page of the target programming sequence must be progammed with actual page program command (10h). figure 10. cache program (available only within a block) 80h r/b 80h address & data input 15h 80h address & data input 15h 80h address & data input 10h t cbsy t cbsy t cbsy t prog 70h address & data input* 15h i/ox col add1,2 & row add1,2,3 col add1,2 data data col add1,2 & row add1,2,3 col add1,2 & row add1,2,3 col add1,2 & row add1,2,3 data data data col add1,2 & row add1,2,3 data "0" "1"
flash memory 34 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m copy-back program figure 11. page copy-back program operation 00h r/b add.(5cycles) i/o 0 pass 85h 70h fail t prog add.(5cycles) t r source address destination address the copy-back program is configured to qui ckly and efficiently rewrite data stored in one page without utilizing an external me mory. since the time-consuming cycles of serial access and re-loading cyc les are removed, the system performance is improved. the ben - efit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly a ssigned free block. the operation for performing a co py-back program is a sequential execution of page-read without serial access and c opy- ing-program with the address of destination page. a read operation with "35h" command and the address of the source page moves the whole 2112byte(x8 device) or 1056word(x16 device) data into th e internal data buffer. as soon as the device returns to read y state, page-copy data-input command (85h) with the address cycles of destination page followed may be written. the program con- firm command (10h) is required to actual ly begin the programming operation. copy-bac k program operation is allowed only within the same memory plane. once the copy-back program is finished, any additional partial page pr ogramming into the copied pages is prohibited before erase. a27 must be the same between source and target page. data input cycle for modifying a portion or multi ple distant portions of the source page is allowed as shown in figure 12. "when there is a program-failure at copy-back operation, error is reported by pass/fail status. but if the soure page has a bit error for charge loss, accumulated copy-back operations could also accumulate bit errors. for this reason, two bit ecc is recommended for copy-back operation. " 35h note : since programming the last page does not employ caching, t he program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cy cle of the last page is initiated only af ter com- pletion of the previous cycle, which ca n be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time) 10h figure 12. page copy-back program operation with random data input 00h r/b add.(5cycles) 85h 70h t prog add.(5cycles) t r source address destination address data 35h 10h 85h data add.(2cycles) there is no limitation for the number of repetition. i/ox i/ox col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 col. add1,2 & row add1,2,3 col add1,2
flash memory 35 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m figure 13. block erase operation block erase the erase operation is done on a block basis. block address loading is accomp lished in three cycles in itiated by an erase setup com- mand(60h). only address a 18 to a 28 (x8) or a 17 to a 27 (x16) is valid while a 12 to a 17 (x8) or a 11 to a 16 (x16) is ignored. the erase confirm command(d0h) following the block addr ess loading initiates the internal erasi ng process. this two-step sequence of setu p followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write controller handles erase and erase-verify. when the erase operation is completed, the write status bit( i/o 0) may be checked. figur e 13 details the sequence. 60h block add. : a 12 ~ a 28 (x8) r/b address input(3cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is complet ed successfully. after writing 70h command to the command register, a read cycle outpu ts the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 fo r specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. table2. read staus register definition note : 1. true ready/busy represents internal program operation status which is being executed in cache program mode. 2. i/os defined ?not use? are recommended to be masked out when read status is being executed. i/o no. page program block erase cache prorgam read definition i/o 0 pass/fail pass/fail pass/fail(n) not use pass : "0" fail : "1" i/o 1 not use not use pass/fail(n-1) not use pass : "0" fail : "1" i/o 2 not use not use not use not use don?t -cared i/o 3 not use not use not use not use don?t -cared i/o 4 not use not use not use not use don?t -cared i/o 5 ready/busy ready/busy true r eady/busy ready/busy busy : "0" ready : "1" i/o 6 ready/busy ready/busy ready/b usy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect write protect protected : "0" not protected i/o 8~15 (x16 device only) not use not use not use not use don?t -care i/ox or a 11 ~ a 27 (x16) "0" "1"
flash memory 36 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m figure 14. read id operation ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar1 t rea read id the device contains a product i dentification mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(ech), and the devic e code and xxh, 4th cycle id, 44h respective ly. the command register remains in read id mode until further co mmands are issued to it. figure 14 shows the operation sequence. device xxh 4th cyc.* ech figure 15. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort thes e operations. the contents of memory cells being altered are no longer valid, as the data will be partially pr ogrammed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin transitions to low for trst after the reset command is written. refer to figure 15 below. ffh i/o x r/b t rst t whr t clr code* table3. device status after power-up after reset pre status high low waiting for next command operation mode first page data a ccess is ready 00h command is latched device device code*(2nd cycle) 4th cycle* k9k2g08q0m aah 15h k9k2g08u0m dah 15h k9k2g16q0m bah 55h k9k2g16u0m cah 55h k9w4g08u1m same as each k9k2g08u0m in it k9w4g16u1m same as each k9k2g16u0m in it
flash memory 37 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m power-on auto-read the device is designed to offer automatic reading of the fi rst page without command and address input sequence during power-on. an internal voltage detector enables auto-page read functions when vcc reaches about 1.8v. pre pin controls activation of auto - page read function. auto-page read function is enabled only when pre pin is tied to v cc. serial access may be done after power-on without latency. power-on auto read m ode is available only on 3. 3v device(k9xxgxxuxm). figure 16. power-on auto-read (3.3v device only) v cc ce cle i/o x ale re we 1st ~ 1.8v pre r/b 2nd 3rd .... n th t r
flash memory 38 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m ready/busy the device has a r/b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/b pin is normally high but transitions to low after pr ogram or erase command is written to the command regis- ter or random read is started after address loading. it returns to high when the internal contro ller has finished the operation . the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropr iate value can be obtained with the follow ing reference chart(fig 17). its value can be determined by the following guidance. v cc r/b open drain output device gnd rp tr,tf [s] ibusy [a] rp(ohm) figure 17. rp vs tr ,tf & rp vs ibusy ibusy tr ibusy busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf voh tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 vol rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + i l = 1.85v 3ma + i l where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + i l = 3.2v 8ma + i l 1.8v device - v ol : 0.1v, v oh : v cc q-0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 c l
flash memory 39 k9w4g08u1m k9w4g16u1m k9k2g08u0m k9k2g16q0m k9k2g08q0m k9k2g16u0m data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase duri ng power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 1.1v(1.8v device) or 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a recovery time of minimum 10 s is required before internal cir- cuit gets ready for any command sequences as shown in figure 18. the two step co mmand sequence for program/erase provides additional software protection. figure 18. ac waveforms for power transition v cc wp high we 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 1.8v device : ~ 1.5v 3.3v device : ~ 2.5v 10 s

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